The payment card industry has developed extremely prescriptive restrictions and guidance regarding how payment devices are to react in the event of suspected tampering. For example, one of the more critical rules states that the cryptographic keys used to perform personal identification number (PIN) encryption and payment data encryption must be automatically and immediately erased following the detection of a tampering event.
Today's computational architectures generally include a single processor with integrated circuitry configured to meet the payment card industry standards related to tamper detection and automated, immediate erasure of sensitive data. Further, due to the single processor nature of the architectures, they often require costly manual processes to initialize, update, and/or manage the various features and encryption keys used during normal operation of the payment device.